The invention broadly relates to non-volatile memory devices, such as flash memories. More particularly, the invention relates to memory devices using a page mode for erase operations, also known as xe2x80x9cpage erasexe2x80x9d, and specifically to the decoding scheme for such operations.
In the FIG. 1A, the flash memory 100 is partitioned into S sectors 102, ranging from sector 0 to sector S. In FIG. 1B, the details of the sector 102 are shown. Each sector 102 further partitioned into J groups, from group 0 to group J. Within each group 112, there are K rows (or xe2x80x9cpagesxe2x80x9d), ranging from row 0 to row K. A row 106 has N memory cells, ranging from cell 0 to N. The first memory cell in a row 106 belongs to column 0 and memory cell N belongs column N respectively. Therefore, there are N+1 columns in the memory array 100. The gates of all the cells within a row 106 are coupled together to form a wordline. The sources of the cells in each row are coupled together and coupled to those of other rows, forming an array source 114. The drains of the cells in each row are coupled together to form a bitline. The NOR flash array 100 allow users to electrically program and erase information stored in a memory cell 108.
Each memory cell 108 in the flash memory matrix 100 is a floating gate transistor. The structure of a floating gate transistor is similar to a traditional MOS device, except that an extra poly-silicon strip is inserted between the gate and the channel. This strip is not connected to anything and called a floating gate. The threshold voltage of a floating gate transistor is programmable. Flash programming occurs when electrons are placed in the floating gate. Programming occurs when a high voltage is applied between the source and gate-drain terminals such that a high electric field causes avalanche injection to occur. Electrons acquire sufficient energy to traverse through the first oxide insulator, so they are trapped on the floating gate. The charge is stored on the floating gate. Flash programming is done on bit-by-bit basis by applying a correct voltage at the bitline 104 of each cell 108.
The floating layer allows the cell 108 to be electrically erased through the gate. Erase operations can be done on more than one cell at a time. Generally, erase is simultaneously done on either the entire flash memory array or an array sector. The erase operation of the entire array is called chip erase, and that of an array sector is a sector erase. Furthermore, erase operations can be performed on a single row in a sector. This is known as page erase.
Referring to FIG. 1C, each memory cell 108 in a row 106 can be set to perform either a source erase or a bulk erase. In a source erase, as in blocks 120 and 122, whenever a row is selected, as in the block 120, the substrate is grounded, the drain is floating, and the source is connected to a positive voltage. The gate is made negative so that electrons are expelled from the floating layer. To avoid an unwanted erase on neighboring rows, unselected rows in block 122 have a ground voltage applied to the gate; the drain is floating; the substrate is grounded and the source is positive. When a row is selected to be erased, a positive voltage is applied at the array source 114; all N columns 104 are allowed to float; the gates of the selected row is made negative and the gates of the unselected rows are applied ground voltage.
For bulk erase, exemplified in blocks 124 and 126, the same voltages as in the source erase blocks 120 and 122 are applied to the memory cell 108, but the only difference is that the source is coupled to the substrate and a positive voltage is applied there.
In either source erase or bulk erase, both addresses of the selected and unselected rows have to be specified. Therefore, large row and column decoders are needed and less memory area is dedicated to memory cells.
The U.S. Pat. No. 6,359,810 entitled xe2x80x9cPage Mode Erase in a Flash Memoryxe2x80x9d to Anil Gupta and Steven Schumann (the ""810 patent) discloses page erase and multiple page erase modes in a flash memory array to reduce unwanted erasure. In the ""810 patent, a preferred tunneling potential of approximately xe2x88x9210 volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias of approximately 1 to 2 volts is applied to the gates of all the flash memory cells in the unselected rows. The ""810 patent uses n-channel MOS transistors as row decoders, and p-channel MOS transistors as pass isolation transistors to isolate unselected rows in other groups from unwanted erasure. The ""810 patent selects a particular row in a group by applying a VCC voltage to that row and zero voltage to other unselected rows in the groups. Other rows in the group are unselected by applying a zero voltage to the drain. Other groups are unselected by applying positive voltage to the p-type channel transistors.
An object of the present invention is to provide page erase operation in a flash memory with protection against unwanted erasure in unselected rows and at the same time does not affect the read access time.
Another object of the present invention is to provide an array architecture with page erase, block erase, and sector erase with minimum die area.
Therefore, it is an object of the invention to optimize the read access time, to optimize the area density of the flash memory 100 dedicated to memory cells, and to provide an ability for the memory to protect unselected cells from unwanted erasure without adding more circuitry.
The above objects are achieved by means of a memory array arranged in rows and columns which are partitioned into a plurality of sectors. Each sector comprises a plurality of groups and each group further comprises a plurality of rows. The row decoder of the memory array is partitioned into local decoders and a global decoder. The local decoders are located in the array sectors and each coupled to each row of the sector for passing a voltage corresponding to a specific operation to each row. Each local decoder further comprises at least one NMOS transistor for passing negative voltage to the row of memory array and a PMOS transistor for passing a positive voltage to the row of the memory array. Each sector of the memory array also comprises local circuitry coupled to the plurality of local decoders for passing the correct voltage thereto. The local circuitry and local decoders, controlled by a global decoder, are only switched during erase operations but not during read operations. Therefore, this arrangement does not affect the reading time. The global decoder is coupled to the local circuitry for passing specific voltages thereto. Because the global decoder is shared by the whole array matrix, more area is saved for memory cells.
In another embodiment, the present invention provides a method for using local decoding scheme with local circuitry and a global decoder to carry out page erase mode in a memory array.